1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including a memory cell in which a charge storage layer and a control gate electrode are configured with an intergate insulating film being interposed therebetween and a method of fabricating the same.
2. Description of the Related Art
A conventional nonvolatile semiconductor memory device comprises a number of memory cells arranged in directions of word lines and bit lines for the purpose of achieving a higher degree of integration. With a recent tendency of higher integration, reductions have been outstanding in a width and length of a memory cell and intervals between adjacent memory cells, whereupon interference is increased between the adjacent cells. An increase in the interference between the adjacent cells results in malfunction of elements and a reduction in a writing/erasing speed.
In order that the interference between adjacent cells may be reduced, a parasitic capacitance between the adjacent cells needs to be reduced, and a facing area of the adjacent cells needs to be reduced, and a height of charge storage layer needs to be reduced. A reduction in the height of the charge storage layer results in a reduction in a coupling ratio that is an index representative of a memory characteristic. In view of this problem, for example, Japanese patent application publication, JP-A-2003-289114 discloses a semiconductor storage device in which a control gate electrode layer is formed so as to face a sidewall of the charge storage layer with an intergate insulating film being interposed therebetween while the height of the charge storage layer is adjusted to a suitable low value, whereby the coupling ratio is improved. Furthermore, when an electrical thickness of the intergate insulating film is reduced, a capacity value between the charge storage layer and the control gate electrode layer can be increased, whereupon a desired value of coupling ratio can be ensured.
However, an electric field applied to an intergate insulating film is increased as the intergate insulating film is thinned. Accordingly, when a high electric field is applied to the intergate insulating film during writing and/or erasing, a leak current of the intergate insulating film is increased to a value substantially equal to a current flowing into a tunnel insulating film. As a result, since the cumulative electron dose is saturated in a charge storage layer, a threshold of memory cell transistor is saturated in a high threshold region.
In order that a capacity value between a control electrode and the charge storage layer may be increased in the nonvolatile semiconductor storage device, for example, Japanese patent application publication, JP-H05-129625 proposes provision of a high dielectric insulating film between the control electrode and the charge storage layer. However, sufficient research has not conventionally been made about the insulating film provided between the control electrode and the charge storage layer.